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EEren
Occasional Contributor
Occasional ContributorMAX10 ADC problem
I created an ADC module in Qsys component adc_qsys is
port (
adc_1_command_valid : in std_logic := '0'; -- adc_1_command.valid
adc_1_command_channel ...
EErenOccasional Contributor
Occasional ContributorThank you very much. Indeed it have to be routed to PLL signal. Now it runs. I see all the signals on Signal Tap but the flag adc1_resp_valid never goes high and adc1_resp_data always zero. May be I do something wrong in the state machine?
