Forum Discussion
EEren
Occasional Contributor
Occasional ContributorMAX10 ADC problem
I created an ADC module in Qsys component adc_qsys is
port (
adc_1_command_valid : in std_logic := '0'; -- adc_1_command.valid
adc_1_command_channel ...
sstrell
Super Contributor
Super ContributorAccording to the user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_adc.pdf) the c0 clock of the PLL is supposed to be dedicated to the ADC, but that doesn't explain why your state machine, clocked by the same clock (G_CLK), is compiling OK without the register file. Does the state machine work without the register file enabled?
#iwork4intel
