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Occasional Contributor
Occasional ContributorMAX10 ADC problem
I created an ADC module in Qsys
component adc_qsys is
port (
adc_1_command_valid : in std_logic := '0'; -- adc_1_command.valid
adc_1_command_channel : in std_logic_vector(4 downto 0) := (others => '0'); -- .channel
adc_1_command_startofpacket : in std_logic := '0'; -- .startofpacket
adc_1_command_endofpacket : in std_logic := '0'; -- .endofpacket
adc_1_command_ready : out std_logic; -- .ready
adc_1_response_valid : out std_logic; -- adc_1_response.valid
adc_1_response_channel : out std_logic_vector(4 downto 0); -- .channel
adc_1_response_data : out std_logic_vector(11 downto 0); -- .data
adc_1_response_startofpacket : out std_logic; -- .startofpacket
adc_1_response_endofpacket : out std_logic; -- .endofpacket
adc_2_command_valid : in std_logic := '0'; -- adc_2_command.valid
adc_2_command_channel : in std_logic_vector(4 downto 0) := (others => '0'); -- .channel
adc_2_command_startofpacket : in std_logic := '0'; -- .startofpacket
adc_2_command_endofpacket : in std_logic := '0'; -- .endofpacket
adc_2_command_ready : out std_logic; -- .ready
adc_2_response_valid : out std_logic; -- adc_2_response.valid
adc_2_response_channel : out std_logic_vector(4 downto 0); -- .channel
adc_2_response_data : out std_logic_vector(11 downto 0); -- .data
adc_2_response_startofpacket : out std_logic; -- .startofpacket
adc_2_response_endofpacket : out std_logic; -- .endofpacket
clk_clk : in std_logic := '0'; -- clk.clk
reset_reset_n : in std_logic := '0' -- reset.reset_n
);
end component adc_qsys;and connected to signals
signal adc1_com_valid : std_logic;
signal adc1_com_channel : std_logic_vector(4 downto 0);
signal adc1_com_startofpacket : std_logic;
signal adc1_com_endofpacket : std_logic;
signal adc1_com_ready : std_logic;
signal adc1_reset_n : std_logic;
signal adc1_resp_valid : std_logic;
signal adc1_resp_channel : std_logic_vector(4 downto 0);
signal adc1_resp_data : std_logic_vector(11 downto 0);
signal adc1_resp_startofpacket : std_logic;
signal adc1_resp_endofpacket : std_logic;
signal adc1_sample_time : std_logic_vector(31 downto 0) := (others => '0');
signal adc1_1_data : std_logic_vector(11 downto 0);
signal adc1_2_data : std_logic_vector(11 downto 0);
signal adc1_3_data : std_logic_vector(11 downto 0);
signal adc1_4_data : std_logic_vector(11 downto 0);
signal adc1_5_data : std_logic_vector(11 downto 0);
signal adc1_6_data : std_logic_vector(11 downto 0);
signal adc1_7_data : std_logic_vector(11 downto 0);
signal adc1_8_data : std_logic_vector(11 downto 0);
signal adc2_com_valid : std_logic;
signal adc2_com_channel : std_logic_vector(4 downto 0);
signal adc2_com_startofpacket : std_logic;
signal adc2_com_endofpacket : std_logic;
signal adc2_com_ready : std_logic;
signal adc2_reset_n : std_logic;
signal adc2_resp_valid : std_logic;
signal adc2_resp_channel : std_logic_vector(4 downto 0);
signal adc2_resp_data : std_logic_vector(11 downto 0);
signal adc2_resp_startofpacket : std_logic;
signal adc2_resp_endofpacket : std_logic;
signal adc2_sample_time : std_logic_vector(31 downto 0) := (others => '0');
signal adc2_1_data : std_logic_vector(11 downto 0);
signal adc2_2_data : std_logic_vector(11 downto 0);
signal adc2_3_data : std_logic_vector(11 downto 0);
signal adc2_4_data : std_logic_vector(11 downto 0);
signal adc2_5_data : std_logic_vector(11 downto 0);
signal adc2_6_data : std_logic_vector(11 downto 0);
signal adc2_7_data : std_logic_vector(11 downto 0);
signal adc2_8_data : std_logic_vector(11 downto 0);
U_ADC : adc_qsys
port map
(
clk_clk => G_CLK,
reset_reset_n => '1',
adc_1_command_valid => adc1_com_valid,
adc_1_command_channel => adc1_com_channel,
adc_1_command_startofpacket => adc1_com_startofpacket,
adc_1_command_endofpacket => adc1_com_endofpacket,
adc_1_command_ready => adc1_com_ready,
adc_1_response_valid => adc1_resp_valid,
adc_1_response_channel => adc1_resp_channel,
adc_1_response_data => adc1_resp_data,
adc_1_response_startofpacket => adc1_resp_startofpacket,
adc_1_response_endofpacket => adc1_resp_endofpacket,
adc_2_command_valid => adc2_com_valid,
adc_2_command_channel => adc2_com_channel,
adc_2_command_startofpacket => adc2_com_startofpacket,
adc_2_command_endofpacket => adc2_com_endofpacket,
adc_2_command_ready => adc2_com_ready,
adc_2_response_valid => adc2_resp_valid,
adc_2_response_channel => adc2_resp_channel,
adc_2_response_data => adc2_resp_data,
adc_2_response_startofpacket => adc2_resp_startofpacket,
adc_2_response_endofpacket => adc2_resp_endofpacket
);Now I want to scan the channels
signal chan : std_logic_vector(4 downto 0) := "00000";
ADC1_SCAN : process(G_CLK)
begin
if rising_edge(G_CLK) then
case Adc1State is
when ST_WAIT_FOR_SAMPLE =>
adc1_sample_time <= adc1_sample_time + '1';
if (adc1_sample_time = X"0000000000989680") then --100 ms
adc1_sample_time <= (others => '0');
Adc1State <= ST_SELECT_CHAN;
end if;
when ST_SELECT_CHAN =>
if (chan = "01000") then
chan := "00001";
else
chan := chan + '1';
end if;
Adc1State <= ST_START_CONV;
when ST_START_CONV =>
adc1_com_channel <= chan;
adc1_com_valid <= '1';
Adc1State <= ST_WAIT_FOR_DONE;
when ST_WAIT_FOR_DONE =>
adc1_com_valid <= '0';
if (adc1_resp_valid = '1') then
Adc1State <= ST_DATA_READY;
end if;
when ST_DATA_READY =>
case chan is
when "00001" => adc1_1_data <= adc1_resp_data;
when "00010" => adc1_2_data <= adc1_resp_data;
when "00011" => adc1_3_data <= adc1_resp_data;
when "00100" => adc1_4_data <= adc1_resp_data;
when "00101" => adc1_5_data <= adc1_resp_data;
when "00110" => adc1_6_data <= adc1_resp_data;
when "00111" => adc1_7_data <= adc1_resp_data;
when "01000" => adc1_8_data <= adc1_resp_data;
when others => Adc1State <= ST_WAIT_FOR_SAMPLE;
end case;
Adc1State <= ST_WAIT_FOR_SAMPLE;
when others => Adc1State <= ST_WAIT_FOR_SAMPLE;
end case;
end if;
end process ADC1_SCAN;And I have a module to read results (with SPI bus)
U_REG_FILE : REG_FILE
generic map
(
SPI_DATA_WIDTH => 8
)
port map
(
REG_CLK => G_CLK,
REG_RST => '0',
ADC1_1_DATA => adc1_1_data,
ADC1_2_DATA => adc1_2_data,
ADC1_3_DATA => adc1_3_data,
ADC1_4_DATA => adc1_4_data,
ADC1_5_DATA => adc1_5_data,
ADC1_6_DATA => adc1_6_data,
ADC1_7_DATA => adc1_7_data,
ADC1_8_DATA => adc1_8_data,
ADC2_1_DATA => adc2_1_data,
ADC2_2_DATA => adc2_2_data,
ADC2_3_DATA => adc2_3_data,
ADC2_4_DATA => adc2_4_data,
ADC2_5_DATA => adc2_5_data,
ADC2_6_DATA => adc2_6_data,
ADC2_7_DATA => adc2_7_data,
ADC2_8_DATA => adc2_8_data
);If I close the U_REG_FILE - it compiles OK. If it's enabled I get
Error (170084): Can't route signal "adc_qsys:U_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1|wire_pll7_clk[0]" to atom "adc_qsys:U_ADC|adc_qsys_ADC_1:adc_1|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|primitive_instance"
What is the problem?
