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Tho_Ge's avatar
Tho_Ge
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4 years ago

MAX10 ADC offset issue

We are using the internal ADC of a Max10 (10M50) to monitor some voltages. For a reference voltage of 2.5V the offset error should be about +/- 5mV (offset error and drift 0.2% FS, prescaler disabl...
Tho_Ge's avatar
Tho_Ge
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4 years ago

Hello,

yes, there are a total of 28 critical errors relating to the ADC. Here is an example:
"Critical Warning (16248): Pin I_FLT_SWITCH_N_AMP2 is placed too close with ADC pins. I / O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: "

The signals that are close to the ADC inputs are mostly static signals that are typically high or low.
Our design uses all IO ports, we cannot leave pins unused around ADC inputs.

Thanks.

Thomas

EngWei_O_Intel's avatar
EngWei_O_Intel
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4 years ago

Hi Thomas

Are you using a development kit or designing a board with Max 10?

And yes, please review all the Critical warning and you can suppress those Critical Warning with IO_MAXIMUM_TOGGLE_RATE set to 0, according to the actual behaviour of those pins.

Also, are you using external Vref? Have you tested with internal Vref?

Thanks.

Eng Wei

  • Tho_Ge's avatar
    Tho_Ge
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    4 years ago

    Hello Eng Wei,

    we don't use a development kit. The measurements were carried out on a dedicated board.

    We also use an external 2.5V reference, as the internal reference is derived from the analog supply voltage and this is not necessarily so stable and accurate.

    See ADC User guide chapter 2.1.6:
    "Intel recommends that you use a clean external voltage reference with a maximum resistance of 100 Ω for the ADC blocks. If the ADC block uses an internal voltage reference, the ADC block is tied to its analog voltage and the conversion result is ratiometric."

    • EngWei_O_Intel's avatar
      EngWei_O_Intel
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      4 years ago

      Hi Thomas

      May I know which board are you using?

      We want to filter out if the external Vref is clean. We assume you have all the power pins reviewed and those power rail has no issue. What is the sample rate is being used? Can you try reducing the sample rate? Reducing the sample rate results in more settling time. It would be interesting to see if this makes a difference. You could refer to Table 25 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_adc.pdf

      Thanks.

      Eng Wei