New Contributor
Frequent ContributorHi there
Are you using a development kit or designing a board with Max 10?
If you are designing a board, have you got the schematic reviewed especially on power and Vref pins? Have you seen similar issue if running the same test on the development kit? Also, please refer to section 3.3 of the userguide for board design guidelines.
Also, can you check if your design compilation having any Critical warning related to ADC?
Thanks.
Eng Wei
New ContributorHello,
yes, there are a total of 28 critical errors relating to the ADC. Here is an example:
"Critical Warning (16248): Pin I_FLT_SWITCH_N_AMP2 is placed too close with ADC pins. I / O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: "
The signals that are close to the ADC inputs are mostly static signals that are typically high or low.
Our design uses all IO ports, we cannot leave pins unused around ADC inputs.
Thanks.
Thomas
Frequent ContributorHi Thomas
Are you using a development kit or designing a board with Max 10?
And yes, please review all the Critical warning and you can suppress those Critical Warning with IO_MAXIMUM_TOGGLE_RATE set to 0, according to the actual behaviour of those pins.
Also, are you using external Vref? Have you tested with internal Vref?
Thanks.
Eng Wei
New ContributorHello Eng Wei,
we don't use a development kit. The measurements were carried out on a dedicated board.
We also use an external 2.5V reference, as the internal reference is derived from the analog supply voltage and this is not necessarily so stable and accurate.
See ADC User guide chapter 2.1.6:
"Intel recommends that you use a clean external voltage reference with a maximum resistance of 100 Ω for the ADC blocks. If the ADC block uses an internal voltage reference, the ADC block is tied to its analog voltage and the conversion result is ratiometric."
