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RS_CEI's avatar
RS_CEI
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1 year ago

Max10 3.3V Differential Input

Product: 10M25DCF484C7G Environment: Quartus Prime Version 21.1.0 Build 842 SJ Standard Edition Max10 3.3V LVDS input. We have a clock on our custom board that is coming in with ~700mV of...
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RS_CEI's avatar
RS_CEI
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1 year ago

Hi AqidAyman! Thanks for the reply.

Design definitely doesn't compile with LVDS (or any differential assignment) on 3.3V VCCIO bank. So you are saying there are two options here:

  1. Adding external circuitry to lower common mode voltage plus swing.
  2. Changing the VCM of the IC sending the clock.

I can DC Block and change the VCM/Swing before the Max10 using external circuitry, but I'm not sure how either of these will allow us to use the differential clock in a 3.3V VCCIO bank.

FvM's avatar
FvM
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1 year ago

Hi,
"So you are saying to change Quartus bank voltage to 2.5V and assign LVDS25? The datasheet specifications on the recommended bank voltage has a maximum of 2.625V (for VCCIO 2.5V) how do you know this will not damage or shorten the life of the part? I would assume the LVTTL/LVCMOS would stay at 3.3V with an actual bank voltage of 3.3V, but are there parts that could get damaged if it is expecting 2.5V I/O?"
As stated, operation is beyond datasheet specs, so I can't guarantee anything. I just mention that it's possible in practice.

Related to output operation, assigned I/O standard is a rule which output transistors out of the available set with different area are activated. With 3.3V actual supply, only smaller current strengths should be enabled although nominal 2.5V VCCIO would allow for larger values. That's particularly important important when driving heavy loads, either resistive or capacitive. IBIS files tell about expectable loaded output current of different I/O standards. Based on this information I conclude that there's no specific risk of operating a 2.5 V output standard with low drive strength at 3.3 V VCCIO.
Related to differential receiver operation there's no useable info in datasheet or device handbook. I can tell that it works, I didn't yet experience damage in 3.3 V operation. Measured common mode range is 0 to 3.3 V, but I don't know worst case margins. Specifically I don't know if there's anything inside the differential buffer that might be overstressed with 3.3 V supply but I won't expect. Surely devices are not production tested under this conditions, so you can hardly expect an official statement approving this operation.

Best regards,
Frank