Forum Discussion
RS_CEI
New Contributor
New ContributorMax10 3.3V Differential Input
Product: 10M25DCF484C7G Environment: Quartus Prime Version 21.1.0 Build 842 SJ Standard Edition Max10 3.3V LVDS input. We have a clock on our custom board that is coming in with ~700mV of...
FvM
Super Contributor
Super ContributorHi,
if you want to operate within specified I/O standards, a resistive divider or AC coupling with bias resistors can bring input voltage into LVDS25 range. It's also possible, although beyond datasheet specifications, to assign LVDS25 to an I/O bank with 3.3V actual supply voltage. According to my observations, input common mode range increases respectively.
if you want to operate within specified I/O standards, a resistive divider or AC coupling with bias resistors can bring input voltage into LVDS25 range. It's also possible, although beyond datasheet specifications, to assign LVDS25 to an I/O bank with 3.3V actual supply voltage. According to my observations, input common mode range increases respectively.
RS_CEINew Contributor
New ContributorHi FvM,
I have other I/O on the bank that does need to be at 3.3V so I can't switch the whole bank over to 2.5V in hardware. So you are saying to change Quartus bank voltage to 2.5V and assign LVDS25? The datasheet specifications on the recommended bank voltage has a maximum of 2.625V (for VCCIO 2.5V) how do you know this will not damage or shorten the life of the part? I would assume the LVTTL/LVCMOS would stay at 3.3V with an actual bank voltage of 3.3V, but are there parts that could get damaged if it is expecting 2.5V I/O?
Thanks for the reply!
