Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

MAX10 - Remote reconfiguration

Hi all,

We have a system which must be updated remotely by a CPU.

I'm able to reprogram the CFM through SPI by the mean of the MAX10 On-chip Flash IP and a SPI to Avalon-MM bridge (I created one because I had troubles with Altera's one...).

The idea is to keep in the first part of CFM one "upgrade configuration" which holds the SPI to Avalon-MM bridge and the On-Chip Flash IP to allow CFM update, and the "application configuration" in the second part of CFM.

I'm also able to remotely switch from one configuration to the other by the help of the Dual-Configuration IP.

The documentation is not clear about all this process of remote reconfiguration, so I would like to know, if somebody can answer those questions:

- It seems I can't use the dual-configuration feature without having the Dual-Configuration IP in the design, right?

- Is it possible to only store both images in the CFM, and just play with the boot_sel pin to change the loaded configuration without implementing that IP?

Thanks in advance for your kind help :-)

Best regards,

Johan

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Maybe I can add some details of the story...

    I would like to write remotely both configuration through SPI from the CPU, then select the one to load by driving the boot_sel pin.

    To do so, I tried to generate single-compressed image for both configurations, then write them in the CFM0 and CFM1 & CFM2 respectively. The FPGA loads configuration from CFM0 but even if I change the boot_sel pin, it still load the configuration from CFM0.

    Then, I tried to implement the dual-configuration IP. From there, I generate dual-compressed image for the "upgrade" configuration. Everything is ok until I generate the .pof file (to get .rpd file for remote flash programming) where a second .sof image is requested (due to the dual-compressed image settings).

    I generate the "application" configuration to be stored in CFM1 & CFM2. I tried to generate it as single-compressed image, but it fails in the .pof file generation of the "upgrade" configuration, until I choose dual-compressed image also for the "application" configuration. So I need to use dual-compressed image also for the application but then I need to also add the dual-configuration IP in the "application" configuration which I don't wan't.

    Johan
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi Johan.

    I know this has been some time. I think you need to have 2 separate designs. design 1 for CFM0 . Design 2 for CFM1 & 2. ( set configuration to dual compressed image ). Only then you can generate the dual compressed pof.

    Design 1 and Design 2 are 2 distinct designs, but from system point of view you can have common interface on both designs so that the MCU will see it as "single" design.

    DUAL CONFIGURATION IP is pretty small ( less than 100 LE I think ). Should be able to fit into spare LE resources ( unless your are using 100% of LE)

    In term of switching from CFM0 to CFM1/2 , you do not necessarily use CONFIG_SEL pin. You can use DUAL_BOOT IP /Dual Configuration IP core user interface to "launch " the app from any CFM ( can be made MCU controlled )

    I agree that documentation on RSU and Dual Boot are a bit challenging, but if you look deep enough, you will find the info that you want.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi,

    Thanks for your reply :-)

    The solution I adopted is the following:

    - As you said, two separated designs, configured as dual compressed image, from which I create a .pof file, with two pages, one for each .sof

    - Dual Configuration IP is instantiated, because mandatory.

    - The connection between CPU and FPGA is SPI, which is connected Altera internal flash controller IP allowing CPU to update one of the two images (one is for appplication, the other for downloading new application, the latter begin read only in flash)

    - The CPU has also control over the configuration pins, including the CONF_SEL allowing dynamic reconfiguration

    It works like a charm.

    Later is better than never, so thanks for you comment :-)

    Johan
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    --- Quote Start ---

    Hi,

    Thanks for your reply :-)

    The solution I adopted is the following:

    - As you said, two separated designs, configured as dual compressed image, from which I create a .pof file, with two pages, one for each .sof

    - Dual Configuration IP is instantiated, because mandatory.

    - The connection between CPU and FPGA is SPI, which is connected Altera internal flash controller IP allowing CPU to update one of the two images (one is for appplication, the other for downloading new application, the latter begin read only in flash)

    - The CPU has also control over the configuration pins, including the CONF_SEL allowing dynamic reconfiguration

    It works like a charm.

    Later is better than never, so thanks for you comment :-)

    Johan

    --- Quote End ---

    I am about start a project with the same exact objective. I have no experience with RSU and would very much appreciate any help that you could provide. Thx Joe
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    --- Quote Start ---

    I am about start a project with the same exact objective. I have no experience with RSU and would very much appreciate any help that you could provide. Thx Joe

    --- Quote End ---

    Hi Joe,

    Please ask, if you need help, maybe I can help you.

    Best regards,

    Johan
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Did you find any application notes that helped with understanding the required process for interfacing to and controlling the Avalon SPI IP to the internal FLASH Controller IP, also I'm not sure I understand the Dual Configuration IP usage. What hardware lines are required to be controlled directly by the host processor for reconfiguring and selecting which config to use? Sorry for what may be stupid questions, I am just getting started and have never used the Qsys utility or Avalon or Nios. I really don't want or need to use Nios (as used in the Altera App note)... just want to control everything through a SPI interface from a processor on a different board.

  • JStag's avatar
    JStag
    Icon for New Contributor rankNew Contributor
    7 years ago

    I have been working with the simple LED Binary and KnightRider example for the I2C RSU slave example on the 10m08sae144eval board. I have built each project using dual compressed image setting and then used the convert programming files utility in Quartus 17 to combine the .sof files into a .pof file with one of the project's sof files directed to be in cfm0 and the other in cfm1. I then load the pof into ​the eval board using a byte blaster. The result is that whichever project is loaded into cfm1 is the one that runs, no matter what setting I put on switch 6 ( that controls the logic level on the bootsel (configsel) pin). I have verified the switch signal is getting through to pin 126 correctly on the max10. If I erase cfm1 then it falls back to running the image in cfm0. I must have a wrong setting somewhere???? Any help would be appreceiated.

  • EEren's avatar
    EEren
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    I didn't understand how I create .rpd file for the second image (CFM1 and CFM2) for downloading it with bootloader.

    As I understand

    1.

    Create a Bootloader Project with Dual Configuration IP core.

    Generate .pof file. (What should I put for the second .sof?)

    Burn the pof file with Byte Blaster on JTAG.

    2.

    Create a Main Project with Dual Configuration IP core.

    Generate .pof file. (What should I put for the second .sof?)

    And now - how I generate the rpd file ??? It dosen't fit the image size !!!