Forum Discussion
Altera_Forum
Honored Contributor
9 years agoHi,
Thanks for your reply :-) The solution I adopted is the following: - As you said, two separated designs, configured as dual compressed image, from which I create a .pof file, with two pages, one for each .sof - Dual Configuration IP is instantiated, because mandatory. - The connection between CPU and FPGA is SPI, which is connected Altera internal flash controller IP allowing CPU to update one of the two images (one is for appplication, the other for downloading new application, the latter begin read only in flash) - The CPU has also control over the configuration pins, including the CONF_SEL allowing dynamic reconfiguration It works like a charm. Later is better than never, so thanks for you comment :-) Johan