Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Max V Hardware Implementation

This is the first time I'm implementing a CPLD and so I came here looking for some advice. The following schematics show how I've wired the JTAG connector and also the bypass caps. I intend to run al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Well, after some hours this is what I came up wth. Caps 1000 and 1001 are large 1000uF caps. Caps 100,101,102 and 103 are 47uF Tantalums.

Note that all the power routed to the decoupling caps is via these caps. Two of the caps are for VCCINT and the other two are for VCCIO. However, each CPLD has two - one for the VCCIO and one for VCCINT. Altera recommend one cap per two IO banks and hence I have one cap.

I'm seeking feedback regarding:

1) Power Distribution

2) Placement of Bulk Caps.

3) Overall routing.

http://i.imgur.com/JtHHm.png

P1 is power for VCCIO and P2 is for VCCINT.