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Altera_Forum's avatar
Altera_Forum
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14 years ago

Max V Hardware Implementation

This is the first time I'm implementing a CPLD and so I came here looking for some advice. The following schematics show how I've wired the JTAG connector and also the bypass caps. I intend to run al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The reason for short wide traces is that long thin traces have higher inductance and, at high frequencies, that inductance becomes high impedance.

If you're only working at low frequencies, there's no need to worry that much about it.

So, I'd still put the 47 µF capacitor. But I wouldn't go to much trouble about trace length and width. I'd just put it somewhere between the power connector and the 1 µF capacitors.