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Altera_Forum's avatar
Altera_Forum
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14 years ago

Max V Hardware Implementation

This is the first time I'm implementing a CPLD and so I came here looking for some advice. The following schematics show how I've wired the JTAG connector and also the bypass caps. I intend to run al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks. I too would prefer a 4 layer board for this job, but there are no PCB manufactures that can do that here. If I want a 4 layer board, I'll have to go to a manufacturer out of the country!

And since this is just a prototype board, that can be a bit cost prohibitive.

My decoupling caps are quite close to the device with a direct connection, so thats taken care of. Do you think I can get away with not having the 47uF cap at all? Will the design be more robust if I choose to include one?

I'm really only concerned about how to distribute power if I do have a bulk cap. Bring a thick trace to the bulk cap and then distribute power to the decoupling caps from that point onwards?

Sort of like this:

http://i.imgur.com/K2bGM.png