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Altera_Forum
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14 years ago

Max V Hardware Implementation

This is the first time I'm implementing a CPLD and so I came here looking for some advice. The following schematics show how I've wired the JTAG connector and also the bypass caps. I intend to run al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Those guidelines are intended to enable reliable high frequency operation; they also kind of assume you have a PCB with GND and power planes.

Of course, for 62 kHz operation, there's much less concern.

But the general idea is to place the capacitors as close to the device as possible, using the shortest widest trace you can, with priority for the small high frequency capacitors.