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Altera_Forum's avatar
Altera_Forum
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14 years ago

Max V Hardware Implementation

This is the first time I'm implementing a CPLD and so I came here looking for some advice. The following schematics show how I've wired the JTAG connector and also the bypass caps. I intend to run al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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is it implying that a pull down resistor is all thats needed to avoid this unknown JTAG state issue.

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Yes, that's the right way.