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Altera_Forum
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14 years ago

Max V Hardware Implementation

This is the first time I'm implementing a CPLD and so I came here looking for some advice. The following schematics show how I've wired the JTAG connector and also the bypass caps. I intend to run al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

JTAG pins are powered by the same VCCIO as the remaining pins on the I/O bank. So, in your case, 3.3V.

I don't have the manuals at hand. The JTAG looks OK but... tripple check.

At higher frequencies, return paths are important and having signals over plane cuts is a problem.

But at 62.6 kHz, it's pretty much a matter of whatever.