MAX V CPLD Reset and OE

Hi ,

Just looked at your code and now i know why the reset is connected to the Data port . Well, there are a couple of issues with the RTL. I don't think its got to do with any Quartus tool settings as the default setting works for most designs.

1. Reset

You've used synchronous reset, ie, Reset is also clocked. This type of reset is tricky to implement and tends to give reset issues. If you're using a system-wide POR (Power-On Reset) you will have to use Asynchronous reset, so that the reset will clear all registers to a known state before the arrival of the clock. In your code, the reset is dependent on the clock pulse, so a POR will not occur. The logic will have to wait till the clock stabilizes from the PLL and then only you can apply the reset. This will lead to reset synchronizing issues between blocks.

** Reset signals are always false-paths in the timing analysis. If you use synchronous reset, then it will also be added into the clock path and will cause timing failures.

Please change your always blocks from

always@(negedge / posedge clock)
if (!reset)

to

always@(negedge clock or negedge reset)
always@(posedge clock or negedge reset)  - IF you want to implement Active Low reset
  if (!reset)
  else
  if()
  end // else
  end //if (reset)  
end //always

2. You are clocking data/signals on both edges of the clock in your block. This will give rise to sync issues. Its always better to have your logic in a single block clock either on posedge or negedge alone and not both. There are cases where you will use both edges, aka , in DDR type designs. For all other purposes, use only one clock edge.

Please make these changes and run the synthesis again. This should solve the reset and clock issues.

-Abr