MAX V CPLD Reset and OE

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Hi eapenabrm,

I try to use another I/O as a reset.

However, I still face the same problem. I try to change the reset to both high and low, however, the output keeps as same.

do you have any idea about the problem?

Thanks!

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Could you post your VHDL/Verilog code. I think the issue may lie how you have assigned and used the reset in the code. If setting a normal GPIO as reset still doesn't work, then the problem may most likely be with the code. You did mention that the Reset is connected to Data pin on the Flops. That is incorrect. For reset to work, it should ideally be connected to the Reset/Rst pin on the DFF and not on the Data pins. Please post your code, will need to take a look at what you're trying to do here.

-Abr