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Altera_Forum
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8 years ago

MAX V CPLD Reset and OE

Hi Guys, I have a problem with the RESET and OE. I noted the MAX V CPLD has assigned pin 44 as DEV_CLR and pin 43 as DEV_OE. I have set pin 44 as my global reset in my design. However, after c...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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I would suggest not using the DEV_CLRn and DEV_OE Pins as these are used during configuration. Try changing the Reset and OE pins to other GPIO and then check. When not using the DEV_CLRn it should be tied high.

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Hi eapenabrm,

I try to use another I/O as a reset.

However, I still face the same problem. I try to change the reset to both high and low, however, the output keeps as same.

do you have any idea about the problem?

Thanks!