Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Max II startup glitch

Hi I have created a PCB using a Max II EPM240T100I5N for a state machine + logic. It works 100% except for the fact that the outputs are high for 100us in duration (1 clock cycle) at startup. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

In verilog HDL,you can use "initial"constructs to implement that.

In setting->Analysis&Synthesis settings->more settings->Ignore Verilog initial constructs->off

This can implement the power up initialization