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Altera_Forum's avatar
Altera_Forum
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17 years ago

Max II CPLD DEV_OE and DEV_CLRn

I'm using MAX-II(EPM1270) CPLD and Here is my question:

How these CPLD DEV_OE and DEV_CLRn pins are asserted and deasserted ??

I red in MAX-II Data sheet that an option has to be set before compilation in the Quartus II software in order to controls these pins,

If I want to use these pins what I have to do and if not what to do?

Please suggest.

Thanks in advance

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The settings can be set in Assignments/Device/Device and Pin Options. It can be found intuitively without reading the Quartus Handbook, I think. (Although the Handbook is always an option).

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,

    I am facing problem during In-system Programming Using the External SPI Master Port.we can see the error below

    Error: Operation failed

    Error: Flash Loader IP not loaded on device 1

    Plz suggest any solution...

    Device used --Cyclon-III (flash EPCS128)

    Tnx & Rgds,

    viru Jawoor
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The solution is to load a design that contains the serial flash loader. You can either include a SFL instance with your design or load the default SFL design for your device, that can be found in the \quartus\common\devinfo\programmer folder.