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Altera_Forum
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16 years ago

Max II CPLD design failing at low temperatures

I have a design that uses an industrial temperature Max II (EPM2210GF256I5). The design is very simple. It does some serial pass-through at 115,200 baud and some at a higher rate (16 x 64kHz). The ma...
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Altera_Forum
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16 years ago

Michael,

my bet would be that you're generating slower clocks from your 20MHz clock and that you're experiencing the effect of hold time time violations due to clock skew.

First, I suggest you use TimeQuest with multi-corner analysis enabled, which should report that your design will fail for the fast timming model.

Second, the following topic has a good explanation of the issues that arise with ripple clocks and alternative solutions

http://alteraforums.com/forum/showthread.php?t=2388