Honored Contributor
Honored ContributorAre you proposing to change the voltage at which the I/O bank in question is powered after initialization, before data transfer? Unusual, but I don't see why it won't work.
You can't really do so without changing the voltage. The MAX device can't drive out at a 1.8V I/O standard if the I/O bank is powered at 3.3V (and vice versa). Driving a 3.3V signal into a 1.8V powered bank is probably not acceptable either - check the datasheet. From memory, you can drive a 3.3V signal into a 2.5V powered bank, but not if it's powered at a lower voltage. Assuming scenario 1, the only* issue I can think of is timing analysis, which Quartus will only do based on one set of I/O signalling standards. So, you'll be operating, in part at least, out of spec. This may not matter. Perhaps your initialization is slow enough such that constraining your design for your data transfer mode of operating is adequate. You'll also have to be careful how you change the voltage on the bank. Check that the bank in question isn't included n the FPGA's POR state machine. Bad behaviour on such a bank's voltage could cause your device to reset. * there may be other issues... Cheers, Alex
