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Altera_Forum's avatar
Altera_Forum
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17 years ago

MAX 7000s JTAG Id Code for Device Error

Hi,

I am a beginner at programming FPGAs. I was working on Altera's "UP2 Development Kit". I have a very simple (and correct) program where I just try to glow 4 segments of the 7-seg display.

However, when I reach the stage where I actually can download the the program to the Max7000s CPLD, I get the following error mesg:

"Error: JTAG ID code specified in JEDEC STAPL Format File does not match any valid JTAG ID codes for device

Error: Operation failed"

I tried to google it, but could not find an answer which could get me up and running. Any help or suggestions welcome and appreciated.

Thanks

vik.vik

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    UP2 has jumpers to connect the JTAG interface either to Flex10K or MAX7000 device. You may have tried to download the design to the wrong chip.

    Quartus programmer can identify and display the connected chip. You should have no problems to figure out which chip is recognized at the JTAG interface.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Thank you, that indeed was the problem, however, the quartus programmer showed that I was connected tp the MAX chip even though the jumpers were not connected properly.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Im a engineer student from Mexico, im actually learning about CPDL by my self. I have an ALTERA MAX EPM7256SRI208-10 and I download from The ALTERA site the Quartus II and Max+Plus II software. I´ve programmed a very simple schematic example program that I compiled and simulated.

    Well I have the USB-Blaster (rev.C) So its only compatible with Quartus II. I configured everything the features for my chip.

    I bought mi CPLD on electronics store, so its new.

    The problem is when I tried to program it, the message that Quartus II displays is: " JTAG ID code specified in JEDEC STAPL Format File does not match any valid JTAG ID codes for device."

    I made a little PCB with the JTAG interface, where the pins are correct and it has the resistences and capacitor well, I connected the chip pins required to VCC= 5 v and ground too. When I click in "auto detect" a message is: "Uncertain JTAG Chain"

    I think the error isnt in my design or features, but why i cant program the CPLD?

    the JTAG isnt enable, but, its NEW??

    The master programming unit (MPU) will enable this feature (is this the Only way)?

    Where where I could get a MPU (will you give me a link) ?

    The MPU is like a universal programmer but for CPLD?

    Have a nice Day everyone!!

    I hope answerss :cool: