Max 10 Unconstrained clock in onchip_flash

I have received a response from support. This is apparently a known issue that is going to be fixed in future versions of Quartus Prime. They are also going to generate a knowledge base entry as well. In order to constrain the flash_se_neg_reg clock you should use the following and modify the path hierarchy to match your design.

create_generated_clock -name flash_se_neg_reg -source [get_pins { blaster:blaster|altera_onchip_flash:max10_onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk }] -divide_by 2 [get_pins { blaster:blaster|altera_onchip_flash:max10_onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q } ]