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Altera_Forum
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9 years ago

Max 10 Unconstrained clock in onchip_flash

I'm working on a design using MAX 10: 10M08SAE144C8G and I'm implementing and I2C RSU circuit. TimeQuest complains of an unconstrained clock as follows:

FLASH_LOADER_CORE:FLASH_LOADER|MAX10_FLASH_INTERFACE:Max10FlashInterface|MAX10_FLASH:FlashModule|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg

Using the Technology Map Viewer is see that this signal is generated by the altera_onchip_flash_avmm_data_controler:avmm_data_controller and is the output of a flip-flop. This signal is then routed into the SE input of the ufm_block.

Can anyone confirm that this is not a clock?

Perhaps I did not properly instantiate the IP?

I want to properly define the constraints for this signal.

Thanks in advance for any assistance.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I have noticed this problem as well. Has anybody submitted a service request to enquire about it?

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I have an open service request for more information on the frequency. If I perform a derive_clock in TimeQuest, it detects this node as a clock. The problem is I'm not sure if this clock setting should be the clock frequency that is input to the RSU or something else. For now, I have used derive_clock and set the period to the frequency input to the RSU so I can move forward while I await a response to my service request.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I found some information in the knowledge database that seems related to this. Do a search using the keywords max10 flash_se_neg_reg. This finds an entry Warning (332060): Node: *altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg was determined to be a clock but was found without an associated clock assignment. That discusses a workaround that may be helpful. I have not tried this yet but may be useful to others.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I have received a response from support. This is apparently a known issue that is going to be fixed in future versions of Quartus Prime. They are also going to generate a knowledge base entry as well. In order to constrain the flash_se_neg_reg clock you should use the following and modify the path hierarchy to match your design.

    create_generated_clock -name flash_se_neg_reg -source [get_pins { blaster:blaster|altera_onchip_flash:max10_onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk }] -divide_by 2 [get_pins { blaster:blaster|altera_onchip_flash:max10_onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q } ]