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LZANU's avatar
LZANU
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2 years ago

MAX 10 programming flow via JTAG

Hi All! I have the following questions about the correct sequence to follow for MAX 10 programming devices via JTAG, especially the 10M04SAU169. 1. I noted that once converted a pof file to SVF and...
Programmable Logic Device
NurAiman_M_Intel's avatar
NurAiman_M_Intel
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2 years ago

Hi,


To confirm, now you are able to remove the verify command, you do not get any error? The design now works fine? The BSDL1532 sequence no longer failed?


Regards,

Aiman