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Occasional ContributorMAX 10 PLL Inverted Output Timing Inquiry
Hi, We are using a MAX 10 PLL in normal mode with an output phase shift of 180 degrees to drive the SCFIFO clock. What is the actual clock-to-clock phase relationship and propagation delay between the original pixel clock and the PLL-inverted output clock at the device pins?
More specifically, is the 180-degree phase shift ideal at the pin level, or should we expect additional PLL insertion delay, jitter, or phase error that must be accounted for in setup/hold timing?
1 Reply
AqidAyman_AlteraRegular Contributor
Hi, at the pin level, you should not assume the clock is exactly 180° from the original pixel clock. In normal mode, the user guide explicitly says the external clock output pin has a phase delay relative to the input clock pin, and that the external output can lead or lag the internal PLL clock signals.
Refer here: https://docs.altera.com/r/docs/683047/21.1/max-10-clocking-and-pll-user-guide/normal-mode
