MAX 10 PLL input and output clocks warnings

Device Max10M40DA256

Nios + SDRAM + application IP on avalon bus

I get warnings on the PLL clocks about the input clock to PLL inclock[0] and an output clock to the SDRAM CK input. Only one PLL is used generating 2 clock outputs. One output for the Nios and one for the SDRAM clk output. Both 100MHz from 25MHz input clk

The PLL input clock is from pin_m3, which is CLK0 input. When built i get warnings for inclock to PLL.

I also get warnings for the SDRAM output clock

How is best to resolve these?

what is the correct way to drive PLL input from external clock input?

what is correct way to generate SDRAM clock from PLL?

Compiler output ..

Warning (15055): PLL "NiosMipr2:u0|NiosMipr2_pll:pll|NiosMipr2_pll_altpll_57g2:sd1|pll7" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
Info (15024): Input port INCLK[0] of node "NiosMipr2:u0|NiosMipr2_pll:pll|NiosMipr2_pll_altpll_57g2:sd1|pll7" is driven by SYS_CLK~inputclkctrl which is OUTCLK output port of Clock control block type node SYS_CLK~inputclkctrl

Warning (15064): PLL "NiosMipr2:u0|NiosMipr2_pll:pll|NiosMipr2_pll_altpll_57g2:sd1|pll7" output port clk[1] feeds output pin "SDRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance