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Ian_Gibb's avatar
Ian_Gibb
Icon for New Contributor rankNew Contributor
5 years ago
Solved

MAX 10 PLL input and output clocks warnings

Device Max10M40DA256 Nios + SDRAM + application IP on avalon bus I get warnings on the PLL clocks about the input clock to PLL inclock[0] and an output clock to the SDRAM CK input. Only one PLL i...
  • Ian_Gibb's avatar
    Ian_Gibb
    5 years ago

    Hi Ash,

    Thanks for this, thats all good now. I also found i had declared the input clock as a global clock which it did not like ... i assume because it no longer exclusive to the PLL input. With that and your notes above i no longer get these warnings.

    Many thanks for your help.

    Ian

Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Ian,


You can assign location to the PLL instance in the Assignment Editor.

1) Go to Assignment Editor.

2) Double click on <<new>> row in To column.

3) Using Node finder, select the PLL instance.

4) In Assignment Name column, choose Location.

5) In Value column, first select the Element as PLL and then the Location as desired.


The PLL_CLKOUT pins are named as B-Bottom, R-Right, L-Left and T-Top based on PLL locations in the package. Please refer Figure 10 of Intel MAX 10 Clocking and PLL User Guide for the PLL locations: https://www.intel.com/content/www/us/en/programmable/documentation/mcn1395213337540.html#mcn1395713558787


Regards.