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StevenBE's avatar
StevenBE
Icon for New Contributor rankNew Contributor
7 years ago

MAX 10 pin status during startup and JTAG programming

What is the status of the IO pins during startup and JTAG programming?

Tristate?

I'm driving NMOS fets with the MAX10. I have to be 100% sure the FETs remain off during startup and programming.

Will a 100K pull-down be sufficient?

3 Replies

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    1. All I/Os pins are tri-stated until device into User- Mode.(It depends on the ICB Values)
    2. Yes, FETs remain off during startup and programming. Weak pullups are often fine for digital input. So you can use pull-up options.
    3. Each I/O pin provides an optional programmable pull-up resistor during user mode. The pull-up resistor, typically 25 kΩ, weakly holds the I/O to the VCCIO level.

    Assignments-> Settings -> Compiler Settings -> Advanced Settings (Fitter) ->Weak Pull-Up Resistor option

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    Yes, You can use ​external pull-down.

    I/O are tristate during JTAG programming.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)

  • StevenBE's avatar
    StevenBE
    Icon for New Contributor rankNew Contributor
    7 years ago

    I'm driving NMOS fets directly from the MAX10.

    So for me tristate with an externall pull-down should work.

    Is it also tristate during JTAG programming?