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StevenBE's avatar
StevenBE
Icon for New Contributor rankNew Contributor
7 years ago

MAX 10 pin status during startup and JTAG programming

What is the status of the IO pins during startup and JTAG programming? Tristate? I'm driving NMOS fets with the MAX10. I have to be 100% sure the FETs remain off during startup and programming. Wi...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Yes, You can use ​external pull-down.

I/O are tristate during JTAG programming.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)