New Contributor
Super ContributorIf you want to use schmitt trigger and slew rate control on same IO bank, have to set VCCIO to 2.5V due to limitation. Else, have to separate them to different bank already.
Why cannot change the IO bank voltage to 2.5V? Since can change to 3.0V already
New ContributorWhy cannot change the IO bank voltage to 2.5V? Since can change to 3.0V already
We cannot power this bank at 2.5V. Some external input signals will reach levels above 3.0V, and we can't easily control that. We could add some kind of voltage level shifting. But this seems overkill and an unnecessary complication just for this purpose.
Thanks for your help anyway.
Super ContributorThe external input signals means the voltage of signals from external device I/O to FPGA I/O bank I/O (powered by VCCIO 2.5V)?
If that's the case, as mentioned by FvM you can don't worry check this https://www.intel.com/content/www/us/en/docs/programmable/683794/current/single-ended-i-o-standards-specifications.html
For example 2.5 V Schmitt Trigger, the VIHmax is VCCIO+0.3=2.5+0.3=2.8V while VILmax is 0.7V. So the maximum input voltage for 2.5 V Schmitt Trigger I/O buffer is VIHmax+VILmax/2=2.8+0.7/2=3.15V
New ContributorThanks ShegN and Frank also, for all the links.
To be honest, I don't like much the idea of powering the bank at 2.5V just for the purpose of getting slew rate control. All the external signals, both inputs and outputs, will connect to 3.3V devices. Even when mixing 3.3V and 2.5V works, is not the ideal condition. I would like to avoid this unless strictly necessary.
We need to review and consider all the implications. I'm wondering if "lying" to Quartus by changing the setting configuration to 2.5V I/O standard, but still powering the bank at 3.3V (or 3.0V) is not the lesser evil here.
Is there any documentation about what actually changes between I/O standard 3.3V, 3.0V, and 2.5V settings? I realize that power and timing analysis would be affected. I also know that some defaults might be changed. But besides that, anything physically changes at the FPGA configuration level?
Thanks,
Super ContributorIf using 2.5V for IO, you can only power the IO bank with VCCIO of 2.5V (not 3.3V or 3.0V). However, the IO pin can receive voltage from external device IO pin up to VIHmax+VILmax/2
