New Contributor
New ContributorMay I know which output voltage do you mean?
Sure. I apologize if I wasn't clear enough.
The hardware is currently working at 3.3V at that I/O bank. I could change it to 3.0V, but I cannot change it to 2.5V.
What I meant is that I know that I could just use the 2.5V I/O standard setting in Quartus, but still leave the actual voltage at the hardware at 3.3 or 3.0V. And this would let me both enable a Schmitt Trigger and slew rate control at the same I/O bank. But this workaround, using a Quartus I/O standard setting that is different than the real hardware, has a couple of problems. One of them is that the timing and power analysis would be wrong.
Hope it is clear now. Otherwise please let me know.
Thanks.
Super ContributorIf you want to use schmitt trigger and slew rate control on same IO bank, have to set VCCIO to 2.5V due to limitation. Else, have to separate them to different bank already.
Why cannot change the IO bank voltage to 2.5V? Since can change to 3.0V already
New ContributorWhy cannot change the IO bank voltage to 2.5V? Since can change to 3.0V already
We cannot power this bank at 2.5V. Some external input signals will reach levels above 3.0V, and we can't easily control that. We could add some kind of voltage level shifting. But this seems overkill and an unnecessary complication just for this purpose.
Thanks for your help anyway.
Super ContributorThe external input signals means the voltage of signals from external device I/O to FPGA I/O bank I/O (powered by VCCIO 2.5V)?
If that's the case, as mentioned by FvM you can don't worry check this https://www.intel.com/content/www/us/en/docs/programmable/683794/current/single-ended-i-o-standards-specifications.html
For example 2.5 V Schmitt Trigger, the VIHmax is VCCIO+0.3=2.5+0.3=2.8V while VILmax is 0.7V. So the maximum input voltage for 2.5 V Schmitt Trigger I/O buffer is VIHmax+VILmax/2=2.8+0.7/2=3.15V
