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Altera_Forum
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8 years ago

Max 10 IO status when Jtag Programming

Hi there, I use Max 10 10M04DAU324 Series FPGA in our design. Only I konw that IO status keeps tri-state with internal weak pull-high when CFM to SRAM(config mode) as attachment picture sh...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi Alex,

No, But I know that ISP Clamp is workable. Discussed with Altera AE, they still test on this problem.

Thanks.