Forum Discussion
Altera_Forum
Honored Contributor
9 years agoMax 10 IO status when Jtag Programming
Hi there, I use Max 10 10M04DAU324 Series FPGA in our design. Only I konw that IO status keeps tri-state with internal weak pull-high when CFM to SRAM(config mode) as attachment picture sh...
Altera_Forum
Honored Contributor
9 years agoAre you using the ISP Clamp feature?
Cheers, Alex