Forum Discussion
Altera_Forum
Honored Contributor
10 years agoI'm using Modelsim though the simulator used doesn't make any difference.
In the Max 10 implementation, the ADC pins aren't exposed in the verilog code so you can't access them directly to feed in a signal which is unfortunate. If it was written differently then for simulation only, then you could have a real data type signal as input to represent the analogue value. There is lots you can do in a test bench to model analogue stuff. In the past I modelled the currents in the inductor of buck switcher which was being controlled by an FPGA. It enabled me to do a complete end to end sim. The analogue stuff was crude but good enough for what I needed. Here is a brief code snippet of the test bench to give you an idea, don't worry about the details of what it does, just get a feel. It recalcs the currents every nanosecond. localparam voltagediffpos = 22.0;
localparam voltagediffneg = 2.0;
localparam inductance = 3.5E-6;
localparam fullscalecurrent = 11.0;
localparam voltagelaser = 1.3;
localparam resistancelaser = 0.05;
localparam capacitancecapacitor = 10E-6;
real current_inductor ;
real current_laser_capacitor ;
real current_laser;
real current_target ;
real voltage_capacitor ;
integer j;
initial begin
for (j = 0; j < 16; j = j + 1) begin
current_inductor <= 0.0;
current_laser_capacitor <= 0.0;
current_laser <= 0.0;
current_target <= 0.0;
voltage_capacitor <= 0.0;
end
end
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin: current_calc
always begin
# 1
current_target <= $itor(voltages)*fullscalecurrent/4096.0;
current_laser_capacitor <= (short_fet) ? 0.0 : current_inductor;
if (buck_fet) begin
current_inductor <= current_inductor + voltagediffpos*1E-9/inductance;
end else begin
if ((current_inductor - voltagediffneg*1E-9/inductance) > 0) begin
current_inductor <= current_inductor - voltagediffneg*1E-9/inductance;
end else begin
current_inductor <= 0.0;
end
end
if (short_fet) begin
voltage_capacitor <= 0.0;
current_laser <= 0.0;
end else begin
if (voltage_capacitor < voltagelaser) begin
current_laser <= 0.0;
end else begin
current_laser <= (voltage_capacitor - voltagelaser) / resistancelaser;
end
voltage_capacitor <= voltage_capacitor + (current_laser_capacitor - current_laser) * 1E-9 / capacitancecapacitor;
end
end
assign comparitor = (current_laser_capacitor > current_target);
end
endgenerate