Matrix Package in VHDL

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This package uses real types.

You could use the integer matrices, but the real matrices are not suitable (real types have no meaning to a synthesisor)

You need to define your own types , in your own package, with the fixed point package.

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I have written the following code and compiled it with Quartus II. It gave me no error... I have also attached the snapshot of compilation page. I think I should use it and see whether I can achieve my result or not. What you suggest?

entity matrix_multiply is port

(

clock : in std_logic

);

end matrix_multiply;

architecture matrix_function of matrix_multiply is

signal i_es_alpha : sfixed(15 downto -12);

begin

multiply: process (clock)

variable matrix_a : sfixed_matrix (0 to 1, 0 to 1);

variable matrix_b : sfixed_matrix (0 to 1, 0 to 1);

variable matrix_c : sfixed_matrix (0 to 1, 0 to 1);

variable resizing : sfixed (15 downto -12);

begin

if rising_edge(clock) then

matrix_a := ((to_sfixed(1,15,-12),to_sfixed(2,15,-12)),(to_sfixed(5,15,-12),to_sfixed(8,15,-12)));

matrix_b := ((to_sfixed(5,15,-12),to_sfixed(2,15,-12)),(to_sfixed(7,15,-12),to_sfixed(8,15,-12)));

matrix_c := matrix_a*matrix_b;

end if;

i_es_alpha <= matrix_c(1,1);

end process multiply;

end architecture matrix_function;https://www.alteraforum.com/forum/attachment.php?attachmentid=10580