Hello, I have one captious question. I need to buil-up matrix adder. Totally 1920x1080=2073600 cells able to do three different operations with 24bit integer value: 1/ A+B=C 2/ A-B=C 3/ IF(A-B) < limit THEN C=1 ELSE C=0 4/ compute sum of all results in all C of all cells to one big 64bit number. Every operation 1,2,3, must be optionaly selectable. Is it possible to do it use of Altera ??? Many thanks :)

Hi Jerry: It depends on what Altera FPGA you'll be using and how fast you need the calculation done. In general, the calculations you are doing are not a big deal, so if it don't need matrix done in a specific time frame pretty much any FPGA that can buffer the matrix data can do the job (or use external ram to buffer the matrix). If you need the results at say every video frame rate, the problem is much more difficult, because you have to do the calculations in parallel, but it's still doable, but may be a much more expensive FPGA. How serial -vs- parallel your calculations are really depends on how fast you need the results. Pete

1920x1080 sounds like HD video. What you want should be doable, but obviously remember you have to stream the data in from somewherem, like external SD ram or something (or maybe even two raw video sources). What is the actual goal.

Hello, yes I am looking for full HD real time parallel matrix processor slice with programmable cells function with 1920x1080 cells. Ideally, it should be able to work at 800 Mhz, 30 frames/sec. Input stream: Parallel data 32(24) bit bus, 2073600 transmissions for every frame, 75Mhz bus clock, asynchronous hi speed FIFO feeding to input latches in altera registers. Output stream: one 64 bt value - long integer. i.e. 30x64=1920bites per sec. That is all. I see, Altera provides no such PLA chip and number of cells on chip is extremly small for such purposes these days. Maybe 1000 yeas in time. I am wonder, no one need such extremly useful tool in the real world. Or have anyone of you any good idea how to do it ? Many thanks.

I dont think you understand what you actually need. The pixel clock rate for 1080p video is only about 75MHz. Why do you need a 800Mhz bus? Why cant you just pass the HD video direct into the FPGA?

Ouh, I am sorry, my mistake... 75. I repaired it yet. :eek::rolleyes::oops: Frame rate is 30 frames per second. Bus clock is 75 Mhz. There is a small problem. I need to process at least 200 pictures per second independently on the basic frame rate from ccd camera. So, 4GHz would be better. :-P Is it possible to buy such one chip solution from Altera ?

Matrix Adder | Altera Community

20 Replies

Altera_Forum
Honored Contributor
13 years ago
I need to create this

http://www.robotics.hiroshima-u.ac.jp/hyper_human_vision/index-e.html

but with a little advanced architecture.
Altera_Forum
Honored Contributor
13 years ago
Looks like a lot of work (and way out of spec for this forum).

I suggest getting down and writing a good spec, get some other engineers involved.
Altera_Forum
Honored Contributor
13 years ago
It is to be replacement of one small part of human vision neural system - part of Cerebellum.

I have software simulation model working ok, but very slow. So I am looking for high speed solution of it. Because I am not able to spread it to real mode, HW accelerator has to be a little faster. I need to compare and compute difference between two pictures 2000x per second.

That is all.

Can you tell me how many reprogrammable cells (adders of A-B or A+B) can I built-up from one Altera chip ?
Altera_Forum
Honored Contributor
13 years ago
there are no reprogrammable cells in an altera chip. Unless you mean how many LUTs and registers there are?

It depends on the device family. Have a look here:
http://www.altera.com/devices/fpga/fpga-index.html
Altera_Forum
Honored Contributor
13 years ago
a - b == a + (-b) == a + (~b + 1) == (a << 1 | 1) + (~b << 1 | 1) >> 1

So changing from add to subtract just involves flipping a bit.

You'll need to treat video data as a linear value stream - not a full frame 2d matrix. It is probably possibly to buffer some adjacent lines.
Altera_Forum
Honored Contributor
13 years ago
So, I think, Stratix V5 FPGA maybe will be suitable. I need 2073600 cells. This FPGA has 359200cells so I need 6 pieces of it. I suppose every cell cal be formed to adder or llimiter. according to the notes 1,2,3 above.

Is it true ?
Altera_Forum
Honored Contributor
13 years ago
That is NOT the way you need to look at it.
Like DSL said, you will NOT be processing the image as a matrix, you will be treating it as a linear stream of data, 1 pixel at a time. So you would only need very few luts and reigsters to do the adition or subtraction. There is no way any of the FPGAs have enough internal memory to store a single HD frame, let alone 1000s. You will be proceing the data as it arrives.

I suggest you go and learn up about digital logic before you move forward. You are completly misunderstanding the architecture of FPGAs.
Altera_Forum
Honored Contributor
13 years ago
I understand. I am seeking for fully parallel system but PLA with 75MHz bus provides serial system, CCD cells would have to be connected to PLA cells directly or whole system will be permanently "serially shaped" and I need only few cells to do such system. OK. Nice. It is fully customer Int.Circ. I can go to grove :(

thank for help
Altera_Forum
Honored Contributor
13 years ago
Dude, go back to the basics like Tricky said. Altera has some on-line free classes about FPGA architecture and digital systems.
Altera_Forum
Honored Contributor
13 years ago
I am not dude :( I am pupil :rolleyes::-P:oops:

be patient I will prepare WEB page of my problem

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Matrix Adder

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