Honored Contributor
Honored ContributorThat is NOT the way you need to look at it.
Like DSL said, you will NOT be processing the image as a matrix, you will be treating it as a linear stream of data, 1 pixel at a time. So you would only need very few luts and reigsters to do the adition or subtraction. There is no way any of the FPGAs have enough internal memory to store a single HD frame, let alone 1000s. You will be proceing the data as it arrives. I suggest you go and learn up about digital logic before you move forward. You are completly misunderstanding the architecture of FPGAs.
