Honored ContributorHello,
I have one captious question. I need to buil-up matrix adder. Totally 1920x1080=2073600 cells able to do three different operations with 24bit integer value: 1/ A+B=C 2/ A-B=C 3/ IF(A-B) < limit THEN C=1 ELSE C=0 4/ compute sum of all results in all C of all cells to one big 64bit number. Every operation 1,2,3, must be optionaly selectable. Is it possible to do it use of Altera ??? Many thanks :)
Honored ContributorHi Jerry:
It depends on what Altera FPGA you'll be using and how fast you need the calculation done. In general, the calculations you are doing are not a big deal, so if it don't need matrix done in a specific time frame pretty much any FPGA that can buffer the matrix data can do the job (or use external ram to buffer the matrix). If you need the results at say every video frame rate, the problem is much more difficult, because you have to do the calculations in parallel, but it's still doable, but may be a much more expensive FPGA. How serial -vs- parallel your calculations are really depends on how fast you need the results. PeteHonored Contributor1920x1080 sounds like HD video.
What you want should be doable, but obviously remember you have to stream the data in from somewherem, like external SD ram or something (or maybe even two raw video sources). What is the actual goal.Honored ContributorHello,
yes I am looking for full HD real time parallel matrix processor slice with programmable cells function with 1920x1080 cells. Ideally, it should be able to work at 800 Mhz, 30 frames/sec. Input stream: Parallel data 32(24) bit bus, 2073600 transmissions for every frame, 75Mhz bus clock, asynchronous hi speed FIFO feeding to input latches in altera registers. Output stream: one 64 bt value - long integer. i.e. 30x64=1920bites per sec. That is all. I see, Altera provides no such PLA chip and number of cells on chip is extremly small for such purposes these days. Maybe 1000 yeas in time. I am wonder, no one need such extremly useful tool in the real world. Or have anyone of you any good idea how to do it ? Many thanks.Honored ContributorI dont think you understand what you actually need. The pixel clock rate for 1080p video is only about 75MHz. Why do you need a 800Mhz bus? Why cant you just pass the HD video direct into the FPGA?
Honored ContributorOuh, I am sorry, my mistake... 75. I repaired it yet. :eek::rolleyes::oops:
Frame rate is 30 frames per second. Bus clock is 75 Mhz. There is a small problem. I need to process at least 200 pictures per second independently on the basic frame rate from ccd camera. So, 4GHz would be better. :-P Is it possible to buy such one chip solution from Altera ?Honored Contributorhold your horses a bit. (no, 4GHZ no nowhere near possible - 300 MHz is on the fast end).
What kind of processing are you doing on these inputs? Your first question has 4 options, all of which would be easily doable in the low end Cyclone chips. You have to remember that FPGAs are massively parrallel processors that can process data in real time. Given your first post requirements there is no need to buffer any data. This is NOT software.Honored ContributorFrame rate from CCD camera (classic WEB camera) can be smaller 15 frames/sec for example, but 30 would be perfect. Normally in working chain every frame has to be preprocessed and PLA must deal with approx. 80x more pictures.
Flow chart: [CCD camera] -> [preprocessing+ creation 80 pictures approx. similar to original picture] -> [for every of 80 picures array A choose the best congruence with fixed picture B (model ] -> output one 64 bit value as asexpression of the best congruence between model B and one of the best suitable picture A. So in every cycle Altera must be able to proceed min. 80x15=1200 frames, 2400 would be perfect. that is all.Honored ContributorDo you want the FPGA to do the pre-processing? What pre-processing is it? and why? And why do you need 80 images.
Your spec is really not very clear.Honored ContributorPreprocessing can be done by classic processor. It is not necessary so as Altera to do it. Altera can express equations mentioned above (1..3)+line 4, but at this case input data stream will be 80x higher i.e. 3.11e9 Int numbers for example. That is all.
Honored ContributorI dont think there are enough IOs or bandwidth in any device anywhere to get that amount of data into the FPGA.
what kind of pre-processing are you doing? and why?
