Matching Xilinx Parallel bit format

I have a contract that has been using Xilinx for a long time. They parallel load the FPGA's by taking the Xilinx HEX formated code and storing it on their system (not Intel HEX format with all the line numbers, semi-colons checksums, etc - just the payload), then read the HEX file and convert it to true binary before putting it out on the 8 I/O lines.

It is not clear which format from the Altera tools will get me closest to the same format and rather then just experiment until I get it right, I thought I would ask here in case someone has already worked all that out.

Thanks,

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