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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Major tool bug

I found a great one today. I tried to generate a VHDL file from a GDF file. The tool reports the following: Warning (275017): Component "FIFO_192" is not instantiated in the "VHDL" design bec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Have you raised a ticket? They dont read their forums.

And why are you using GDF files? they were last used in Max Plus 2?