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oooh, so this means that adding "after 30 ns" will be ignored. actually, what is the use of "after 30ns"? some vhdl books have included this line into their commands. i thought it can some how delay the result?
i've design a component which works on asynchronous inputs however, those inputs to the component are clock driven. how can i ensure that my final result becomes an asynchronous result?
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It is valid VHDL but for behavioural code only i.e. testbenches etc. It is not valid for RTL coding and hence synthesize.
It is virtually impossible to synthesize something like a delay line into an FPGA architecture
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