maintaining my result from becoming unknown state

hi mikedsouze,

the "after 30ns" is for pre-synthesis simulation or generating test benches as input stimulus for pre or post-synthesized VHDL.

from the comp.lang.vhdl faq (http://www.eda.org/comp.lang.vhdl/faq1.html):

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After clauses in signal assignment statements are not synthesised as there is no hardware primitive that has a fixed but settable delay. (Usually the delay varies significantly with temperature, supply voltage, output loading and the like). In the best case they are ignored by the synthesis tool. Hence, the statement

sig <= not sig after 10 ns;

will not result in an inverter with a 10 ns delay. Most likely, an inverter will be synthesized, but no attempt is made to adhere to the delay specification.

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to get a stable output you will want to read about clocked processes and inferring flipflops.