LVDS SERDES Routing problems

Since I am using the SERDES receivers in DPA mode and the refclkin should be connected to an IOPLL, I have changed the constraint for the high speed clock to an input (as described in the documentation) that connects to an IOPLL.

However, this time the Fitter generates an error for an invalid placement. See errors below:

Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (150, 36) to (150, 44), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): adc1_dco
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (18805): No dedicated path available for refclk signal, adc1_dco. Please promote your refclk to a global clock or move it to a dedicated IOPLL refclk pin. (1 location affected)
Info (175029): pin containing PIN_R2
Info (175015): The I/O pad adc1_dco is constrained to the location PIN_R2 due to: User Location Constraints (PIN_R2)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (84, 9) to (84, 17), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): adc2_dco
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (18805): No dedicated path available for refclk signal, adc2_dco. Please promote your refclk to a global clock or move it to a dedicated IOPLL refclk pin. (1 location affected)
Info (175029): pin containing PIN_AC16
Info (175015): The I/O pad adc2_dco is constrained to the location PIN_AC16 due to: User Location Constraints (PIN_AC16)
Info (14709): The constrained I/O pad is contained within this pin
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 10 errors, 73 warnings
Error: Peak virtual memory: 6608 megabytes
Error: Processing ended: Mon Feb 03 17:21:59 2025
Error: Elapsed time: 00:01:13
Error: Total CPU time (on all processors): 00:01:09

I am attaching the A10_Handbook Figure for SERDES with DPA enabled, which I use for the LVDS SERDES IP, and screen capture of the PIN PLANNER with the SEDRDES IP pin inputs.