Forum Discussion
Occasional ContributorLVDS Serdes in Cyclone 10 LP and GX devices
Hi,
Cyclone 10 LP datasheet
Table 27. True LVDS Transmitter Timing Specifications for Intel Cyclone 10 LP Devices
Table 29. LVDS Receiver Timing Specifications for Intel Cyclone 10 LP Devices
Cyclone 10 GX datasheet
Table 37. High-Speed I/O Specifications for Intel Cyclone 10 GX DevicesImportant feature of Cyclone 10 GX LVDS receiver is DPA and CDR capability, synchronize to serial data stream without external clock.
All documents can be found here https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/fpga-developer-center.html
Super ContributorHi,
Cyclone 10 LP datasheet
Table 27. True LVDS Transmitter Timing Specifications for Intel Cyclone 10 LP Devices
Table 29. LVDS Receiver Timing Specifications for Intel Cyclone 10 LP Devices
Cyclone 10 GX datasheet
Table 37. High-Speed I/O Specifications for Intel Cyclone 10 GX Devices
Important feature of Cyclone 10 GX LVDS receiver is DPA and CDR capability, synchronize to serial data stream without external clock.
All documents can be found here https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/fpga-developer-center.html
