LVDS SERDES doesn't work

I'm using Arria-10 to make a LVDS SERDES. But it doesn't work. Looking forward to your help.

signal FL_Clk        : std_logic;
signal FL_Channel0   :  std_logic_vector(6 downto 0) := (others => '0');
signal FL_Channel1   :  std_logic_vector(6 downto 0) := (others => '0');
signal FL_Channel2   :  std_logic_vector(6 downto 0) := (others => '0');
signal FL_Channel3   :  std_logic_vector(6 downto 0) := (others => '0');
    
signal LVDSOut       :  std_logic_vector(4 downto 0) := (others => '0');  -- LVDSOut(3 downto 0) = Channel 0..3    LVDSOut(4) = Clock
i0_Serdes : SERDES        port map (
            tx_in        => FL_Channel3 & FL_Channel2 & FL_Channel1 & FL_Channel0,        --        tx_in.export
            tx_out       => LVDSOut(3 downto 0),       --       tx_out.export
            tx_outclock  => LVDSOut(4),  --  tx_outclock.export
            inclock      => Clk_125mhz,      --      inclock.export
            --pll_areset   => Reset,   --   pll_areset.export
            pll_areset   => Reset_flu,
            pll_locked   => open,   --   pll_locked.export
            tx_coreclock => FL_Clk  -- tx_coreclock.export
        );
-- Output
g_out: for i in 0 to 4 generate
    i_out: diff_out
    port map(
        din       => LVDSOut(i downto i),
        pad_out   => localdisplay_dp(i downto i),
        pad_out_b => localdisplay_dn(i downto i)
    );    
end generate;