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Altera_Forum
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15 years ago

LVDS Sampling Data

Hi all, I have on my board double data rate (DDR) LVDS bus samped by clock of 168Mhz. I sampled the LVDS bus using ALTDDIO mega function. The problem is that i have skew between clock and data...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm not following. ext_clk is the virtual external clock. The set_input_delay applies the assignment to the input pins(you have to change the name to match your pin names). The default setup relationship between ext_clk and fpga_clk is 5.942ns. A multicycle -setup 0 will make it 0ns. If you run report_timing on the paths, it will tell you what the setup and hold relationships are.