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Honored Contributor
Honored ContributorLVDS Sampling Data
Hi all, I have on my board double data rate (DDR) LVDS bus samped by clock of 168Mhz. I sampled the LVDS bus using ALTDDIO mega function. The problem is that i have skew between clock and data...
Altera_ForumHonored Contributor
Honored Contributorfpga_clk is the clock coming into the FPGA that drives the input registers. I think it was the first line in the sample .sdc.
