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Honored Contributor
Honored ContributorLVDS Sampling Data
Hi all, I have on my board double data rate (DDR) LVDS bus samped by clock of 168Mhz. I sampled the LVDS bus using ALTDDIO mega function. The problem is that i have skew between clock and data...
Altera_ForumHonored Contributor
Honored ContributorThanks, you are the best.
If I want to use multicycle solution, should I define fpga_clk? and what fpga_clk means?
